Methodology:

Design Verification
Mobiveil follows a robust in-house design guidelines that addresses both ASIC and FPGA needs. The guideline accounts for Synthesis/DFT friendly and Low Power designs. Process-wise, the guidelines takes into account, the handshake required with different teams like PD, DFT, Verification and Validation. A separate Lint and CDC process guideline enable designers to deliver a first time right design. Mobiveil follows a robust in-house design guidelines that addresses both ASIC and FPGA needs. The guideline accounts for Synthesis/DFT friendly and Low Power designs. Process-wise, the guidelines takes into account, the handshake required with different teams like PD, DFT, Verification and Validation. A separate Lint and CDC process guideline enable designers to deliver a first time right design.

Our high level verification flow is given below:

ASIC_design

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