“Avago Technologies is a leading provider of high-speed serial transceiver (SerDes) technology and silicon solutions for wireless and wired communications infrastructure equipment,” said Harold Gomard, Director of Technical Marketing, Avago. “Our customers can leverage fully-verified RapidIO Gen3 interface solutions based on Avago SerDes and Mobiveil controller IP.”

“Mobiveil’s RapidIO 10xN design win demonstrates that wireless infrastructure applications are migrating to next generation RapidIO designs,” said Rick O’Connor, Executive Director at RapidIO.org. “We are currently working on extending the RapidIO protocol for next generation communications infrastructure and for rapidly growing data center applications. We are pleased to see Mobiveil’s continued effort to make fully integrated RapidIO IP available to its customers.”

“Mobiveil’s UNH certified NVM Express IP helps us keep pace with the complexities of this new standard without dedicating our own engineering resources to do so,” said Dmitriy Gusev, CEO of CloudWave. “We chose Mobiveil NVMe IP because of its feature set, configurability, protocol certification record, extensive system level validation process and efficient technical support. This enables our engineers to concentrate on building value-add features of our product that will provide our customers the fastest and efficient solution for boosting their storage system.”

“Access to Mobiveil’s UNH certified NVM Express IP helps us keep pace with the complexities of this new standard and integrate our new generation SOC devices for the mobile storage market,” said Kevin Yeh, Vice President of Algorithm and Technology at Silicon Motion. “We chose Mobiveil because its IP Architecture, Configurability, protocol certification record, extensive system level validation process and superior technical support. This will enable our designers to focus their efforts on delivering differentiated products to the market.”

Serial RapidIO (SRIO) is a key technology that is widely used as chip-to-chip interface in wireless communication applications. Mobiveil is actively involved in the definition and deployment of this technology worldwide. With its insight into this technology, Mobiveil developed a state-of-the-art, highly configurable, Serial RapidIO interface IP (GRIO™) with AXI Interface (RAB™) that operates at 6.25Gbps. Last year, LSI selected this IP as the SRIO interface for its Axxia 5500 family of communication processors.

“Implemented in the smallest area with the industry’s lowest power consumption, the Mobiveil LDPC technologies exploit the actual physics-based flash device characteristics to extend the durability of the flash memory,” declared Andrei Vityaev, Member of Mobiveil’s Advisory Board. “The Mobiveil LDPC IP dramatically extends the endurance and retention of NAND Flash and other block-based memories compared to currently available solutions, enabling next-generation solutions to use 1x/1y/1z nm, 3D technologies with significantly improved reliability and endurance.”

“Our collaboration with Mobiveil will offer SoC designers a combined PHY and controller for PCIe 3.0 technology,” said Semtech Corp. Worldwide Marketing Director, Snowbush IP, Kevin “Semtech’s endpoint PHY IP for PCI Express 3.0 technology passed PCI-SIG® compliance testing and is now on the PCIe 3.0 Integrators List. It can support both long reach and short reach channels. The Snowbush PHY for PCIe 3.0 technology delivers high performance with best-in-class power efficiency in process nodes down to 28nm. This saves in-house engineering and frees these resources to concentrate on value added circuit design.”

“We look forward to having Mobiveil support Spansion’s HyperBus memory solutions,” said Jackson Huang, vice president of product marketing and ecosystem at Spansion. “Combining the high performance MirrorBit® architecture with the low pin-count nature of the HyperBus interface, Spansion’s HyperFlash memory achieves the industry’s highest read throughput, up to 333 megabytes per second. That’s more than five times faster than ordinary quad SPI flash currently available with one-third the pin-count of parallel flash. The balance of high performance and low pin-count makes HyperFlash memories especially attractive for applications, including automotive instrument clusters, infotainment/navigation systems and advanced driver assistance systems (ADAS).”

“M31 is delighted working with Mobiveil to achieve a compliant PCIe 2.0 IP solution which serves our growing customer base in Asia,” said M31 Technology Corp. Chairman Hsiao-Ping Lin. “Engineering a PCIe 2.0 PHY, because of its high speed, requires specialized engineering expertise. Our PHY eases integration and silicon validation. The IP also provides compact die size and pad counts to increase the competitiveness of SoC designers’ PCIe 2.0 applications. Our PHY IP operates on 1.2V to ensure designers have no power distribution issues and it supports PCIe PIPE power-saving modes P0, P0s, P1, and P2 for ultra-low power operation. The PHY’s adaptive equalizer minimizes wide range channel loss.”