Mobiveil’s OCTA PSRAM controller supports Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.

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Gen1/2/3 RC Controller with SRIOV

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