Memory Controller

Interface IP

Memory Controller

Flash Storage

System-on-chip

DDR4/3, LPDDR
DDR5
Octa PSRAM
Winbond HyperRAM

UFSHC

Overview

Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.

  • Compatible with following Xccela PSRAM devicesfrom APMemory ⋄ 8 bit data bus - DQ[7:0] support for APSxx08L-0B device, where xx stands for memory density ⋄ 16 bit data bus - DQ[15:0] support for APSxxyyN device, where yy stands for I/O config ⋄ Possible values: xx=64, 128, 256 and yy=08, 16
  • Compatible with APS3208K device from APMemory
  • Memory mapped access to the connected PSRAM Device
  • Octal SPI Interface with DDR mode access support
  • Wrap transfer support
  • Continuous mode Burst transfer support for efficient memory access
  • Hybrid wrap burst transfer support
  • APB port for control registers accesses
  • Read-Prefetch feature for efficient read data throughput in AHB-Lite flavour
  • AXI4 system interface for memory access with outstanding address support. Alternatively, AHB Lite system interface for memory access
  • Half sleep and deep power down control through simple CSR access
  • Behavioral reference PHY model for easier technology specific integration and implementation
Octal PSRAM block diagram
Design Attributes
• Highly modular and programmable design • Fully synchronous design • Software control for key features
Product Package
• RTL Code • System Verilog/UVM based Testbench • Test cases • Protocol checkers and bus watchers
Documentation
• Design Guide • Verification Guide • Synthesis Guide
Licensing Options
• Single Design or Multi-project license (HDL Source Code)

Get the Detailed Product Brief here

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OCTA PSRAM
OCTA PSRAM
Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.
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