Memory Controller
Interface IP
Memory Controller
Flash Storage
System On Chip
Overview
Overview
Overview
Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.
Overview
Mobiveil’s HyperRAMTM controller supports Winbond’s HyperBus
based HyperRAMTM devices which are used in following applications:
- IoT
- Consumer devices
- Automotive
- Industrial
This controller enables smooth integration of Winbond’s HyperBus
HyperRAMTM memory chips into various new-gen SoCs’.
The controller is designed using Technology independent Verilog RTL and
supports all industry standard Simulator, Synthesis and Lint/CDC tools.
Overview
Most wearables devices typically monitor a finite set of
parameters which does not demand a lot of computing
power and memory size. Thus any wearable design
requires low power, lower RAM density and simplified
interface with optimal performances. These design
requirements make PSRAM a natural choice for wearable
applications.
