LDPC

Overview

Mobiveil’s LDPC Encoder / Decoder* is a flash reliability solution delivering industry-leading flash endurance and retention through advanced LDPC error correction coupled with statistical digital signal processing (S-DSP) at the lowest power and smallest foot print. LDPC incorporates these advanced technology in to a highly scalable flash media side platform that can be tailored to customers specific application requirements from smart phones and tablets that require ultra-low power consumption to SSDs for enterprise computing applications that demand the highest performance.
  • Patented technology delivers the industry’s highest reliability, highest performance, and lowest power for next-generation flash controllers
  • Dramatic increases in P/E cycles significantly extends the life of flash memory
  • Addresses the reliability challenges of MLC, TLC and 3D Flash at 1y and 1z nm geometries
  • Access to flash manufacturer’s test mode commands to enable the generation of soft information for optimal reliability performance
  • LDPC IP scalability
  • Supporting a wide range of data-rates
  • 50MB/s to 9.0GB/s for a single LDPC instance
  • Scalable platform provides the basis for customer specific custom-LDPC cores
  • Each LDPC IP is optimized for
  • Codeword size, supports wide range of codewords
  • Maximum amount of supported parity
  • High degree of parallelism for high data-rate applications
  • Different Memory access options
  • Platform specific options (eASIC, FPGA, 40nm ASIC, 28nm ASIC, 16nm ASIC, 10nm ASIC)
  • All LDPC IP Cores share the following features
  • Simultaneous support for different amounts of parity
  • Simultaneous support for several LDPC codes
  • On-the-fly switching from one LDPC code to another
  • Low area and power
  • Patented technology delivers the industry's highest reliability, highest performance, and lowest power for next-generation flash controllers
  • Dramatic increases in P/E cycles significantly extends the life of flash memory
  • Addresses the reliability challenges of MLC, TLC and 3D Flash at 1y and 1z nm geometries
  • Access to flash manufacturer's test mode commands to enable the generation of soft information for optimal reliability performance
LDPC block diagram
Licensing Options
• LDPC • NVMe (UNEX) + LDPC + Enterprise Flash Controller
Product Package
• Source Code for LDPC Compiler • Source Code for LDPC Matrix Generation Software • FPGA based LLR generation reference design with MATLAB interface • UVM verification env with encoder, error injector and decoder instantiated
Documentation
• IP User Guide • Synthesis Guide

Get the Detailed Product Brief here

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OCTA PSRAM
OCTA PSRAM
Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.
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