Consulting services

  • Early feasibility analysis to help customer, conclude on feature sets and high level architecture of their ASIC/FPGAs
  • Enabling IP/Silicon ‘Compliance certification’ for industry standards like USB 3.0, PCI-Express, DDRx, and NVM-Express
  • Enabling accelerated closure of designs to ‘Production Quality’
  • ‘IP Packaging’ of SOC blocks for reusability and license-ability
  • Turnkey Solutions

Standalone services

  • Multi-million ASIC Implementation – Design/Integration, Linting, CDC and Synthesis
  • Coverage driven & Power/CDC aware functional verification
  • FPGA Emulation in Stratix V and Virtex/Artix-7 Devices

Specialized Domains

  • Flash Storage – Strong in storage protocols and systems.
    • NVM-express, AHCI, SOP, SATA
    • High density FLASH storage & Hybrid memory systems
  • High speed interconnect – PCI-Express, USB 3.0, SRIO
  • Memories – DDR4/3, LP-DDR3/2
  • Video – HDMI & MIPI
  • SOC FPGAs – Zynq, Arria, Cyclone-V

Differentiated Advantages

  • ‘Production Proven set of IPs & VIPs’ enabled services – Reduces overall product timeline
  • License/Royalty free SOC reusable components and BFMs – Reduces overall development cost

 

Contact Sales@mobiveil.com for more information.

VIP Portfolio*   &   ‘VIP Enabled’ Verification Services:

VIP costs, complexity, and stringent licensing models can aggravate getting good Return on Verification (ROV). Mobiveil and Avery Design Systems offer a rich set of ‘Production Proven VIPs’ in flexible licensing models to customers. Coupled with ‘IP Compliance Testsuite’ and ‘VIP Enabled’ Verification Services, we help customer cut the project schedule, reduce the NRE cost significantly while improving verification closure.

VIP Portfolio:
High Speed IO PCIe
SR-IOV
M-PCIe
USB
xHCI
SSIC/HSIC
OTG
AXI4/ AXI3
AHB
ACE
SRIO Gen3
SRIO Gen2
SSD/HDD NVMe UAS/BOT SCSI Express (SOP/PQI) SATA Express (AHCI)
SATA
Embedded Storage UFS
UFSHCI
eMMC HC
eMMC Device
SD HC
SD Device
UHS-2
Mobile UniPro M-PHY D-PHY
Memory DDR4/3/2
LPDDR3/2
DFI-PHY
RDIMM
LRDIMM
HMC ONFI
Toggle 1/2
Control Bus CAN
CAN FD
I2C
QuadSPI
UART
SMBUS
‘VIP Enabled’ Verification Services:
  • VIP Integration and Bring-up @ IP, Subsystem, SOC Level
  • Work with customer to investigate DUT bugs
  • Verification using compliance test-suite
  • Enhanced functional and connectivity verification
  • Performance and latency measurement
  • Emulation/Validation support of corresponding protocols
  • Work with customer on product certification

* – Under License from Avery Design Systems

 

Contact Sales@mobiveil.com for more information.

Methodology:

Design Verification
Mobiveil follows a robust in-house design guidelines that addresses both ASIC and FPGA needs. The guideline accounts for Synthesis/DFT friendly and Low Power designs. Process-wise, the guidelines takes into account, the handshake required with different teams like PD, DFT, Verification and Validation. A separate Lint and CDC process guideline enable designers to deliver a first time right design. Mobiveil follows a robust in-house design guidelines that addresses both ASIC and FPGA needs. The guideline accounts for Synthesis/DFT friendly and Low Power designs. Process-wise, the guidelines takes into account, the handshake required with different teams like PD, DFT, Verification and Validation. A separate Lint and CDC process guideline enable designers to deliver a first time right design.

Our high level verification flow is given below:

ASIC_design

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On March 27-03-2017

 

Mobiveil has crossed an important milestone of completing 5 years of its Journey

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Thanks to our Investors, Customers and Employees, we are growing stronger year over Year…

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Gen1/2/3 RC Controller with SRIOV

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