AXI Matrix

The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs. AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4.


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Key Features of AXI MATIX-IP:

  • Configurable Number of AXI Master ( Slave interface SI) ( 1-16) ( S0…S15)
  • Configurable Number of AXI Slave ( Master Interface MI) (1-16) ( M0…M15)
  • AXI Address Width ( 32 or 64)
  • AXI Data width (32, 64, 128, 256, 512)
  • AXI Slave ID width (MAS_ID_WIDTH + log2(AXI_Master_ID_WIDTH)
  • AXI BURST WIDTH (16 beats for AXI 3 and 256 beats for AXI4)
  • Configurable UP Sizer/Down Sizer for Master (SI)
  • Configurable UP Sizer/Down Sizer for Slave (MI)
  • Configurable Read acceptance Capability for the Master(SI)
  • Configurable Write acceptance Capability for the Master(SI)
  • Configurable Read issuing Capability for the Slave (MI)
  • Configurable Write issuing Capability for the Slave(MI)
  • Arbitration scheme at MI interface( to Slave Port) Round robin
  • Arbitration scheme at the SI interface (to Master port read /write response) Round robin.
  • Asynchronous Clock support for Master Interface (SI ) and Slave Interface (MI)
  • Out of order support for write response limited to 4 bit ID width (max 16 IDs).
  • Out of order support for read response/data limited to 4 bit ID width (max 16 IDs).
  • Multiple REGION support for SOC slaves
  • TrustZone Security feature support for Connected Slaves
    • It only permits, if the slave is configured as secured slave.
    • Any Non secure transactions to the secure devices are blocked and it turns with DECERR response to the connected master.
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